The competitors between Intel and AMD has been heating up in the previous few years as Intel has launched chips fabbed with their 14nm++ course of and AMD has been utilizing TMSC’s 7nm course of. Within the wake of the 2 semiconductor titans clashing, a debate between the deserves of 14nm++ and 7nm has sprung up with some confusion about what these numbers really measure. Not taking both quantity at their face value, [der8auer] determined to extract a transistor from each Intel’s and AMD’s newest choices to attempt to shed some gentle.
A lot of the confusion comes from the swap to the FinFET course of. Whereas older planar transistors might be considered largely second buildings, FinFET’s are three dimensional. Which means that the entire vertical fin can act as a gate, enormously decreasing leakage. It’s this fin or gate that [der8auer] is after. On every chip, a skinny sliver from the L1 cache was chosen as caches are typically pretty homogenous sections with transistors which might be pretty indicative of the remainder of the chip. Beginning with a platinum gasoline intersecting with a centered ion beam on the floor of the chip, [der8auer] constructed a small deposit of platinum over a number of hours. This layer protects the chip when he later lower it at an angle, forming a small lamella 100 micrometers lengthy. To ensure that the lamella to be correctly imaged by the scanning electron microscope, it wanted to be even thinner (about 200 to 300nm).
Ultimately, [der8auer] was in the end in a position to measure the gate peak, width, spacing, and different elements of those two chips. The sheer quantity of engineering and evaluation that went into this undertaking is outstanding and we love the deep dive into the precise gates that make up the processors we use. If you happen to’re on the lookout for a deep dive into the heart of a processor however maybe at a extra macro scale, why not find out about a forgotten Intel chip from the 1970s?
Thanks [paulvdh] for sending this one in!
